1. Field of the Invention
This invention relates to a variable pulsewidth gated clock generator and more particularly to such a generator for the provision of timing signals in a digital display unit.
2. Description of the Prior Art
In order to reduce the manufacturing costs of the circuitry for a digital display unit, it is desirable to achieve as many functions on a single integrated circuit chip as permissible, either by increasing the packing density of the gates in the chip or by novel circuit designs and architecture creation. This in turn leads to wider use of the digital display units to in turn accommodate more applications for information processing systems.
Such digital display units may be custom made or may be formed of conventional commercial television sets. In either case, the information displayed is usually of the nature of characters formed of dot matrix where the display unit employs a raster scan mode. Each horizontal line is divided into a number of discrete points or areas called picture elements (PELS) or pixels. A fraction of such picture elements per line is not employed for information display but is that portion of the scan time required for horizontal retrace and synchronization of the horizontal oscillator.
As the display screen is scanned, the dot matrix characters are formed by character generation circuits that control the modulation of the electron beam (in the case of CRT displays), individual circuits of which are selected by character codes that are stored in the memory. This code store can be a shift register with exactly the same number of cells as there are character positions on the display screen, or it may be a random access memory.
In some display units, 25 to 30 complete scans of all the lines making up the display are made per second. Thus, each portion of a character being displayed is on display 25 to 30 times a second for a brief period and this can cause an apparent flickering. The flickering problem is normally solved by refreshing or redrawing all the lines in the display in two consecutive interlaced scans. A "half-scan" is redrawn or refreshed in half the time. Because of the 2:1 interlace between the two half-scans, if a horizontal line is drawn in one half-scan and is adjacent to a line drawn in the next half-scan, the two form a line on the display screen with reduced flicker because, in essence, it is written twice as often. Applying this knowledge, 6.times.8 dot matrix character can be displayed on a 12.times.16 dot matrix, by displaying each dot in the 6.times.8 matrix four times. This reduces flicker considerably, as the character now seems to be written 50 to 60 times a second, instead of 25 to 30 times.
In order to supply such elements of information to the video output circuit to create a complete display in a commercial video monitor, it is necessary that the respective registers and gates in the video output circuit and the buffer circuit be driven by a very fast clock, of the order of magnitude of 12 megahertz or higher. Since the respective video output circuits and buffer circuits are implemented in integrated circuit silicon chips, the respective circuits are driven by an external clock of appropriate frequency. However, many of the clock signals required to drive the respective circuits may not be of the same time duration as are the high speed external clock signals. Therefore, it is desirable to be able to provide a clock generator that is driven by an external clock but can nevertheless vary the output clock signal in a manner determined by logic internal to the integrated circuit chip. It is, therefore, an object of the present invention to provide an improved gated clock generator for employment with the video output circuit of a digital display.
It is still another object of the present invention to provide a gated clock generator, the output pulsewidth of which may be varied as required.
It is still another object of the present invention to provide a gated clock generator which can operate at the frequency of an external clock and yet provide enough power to drive the various circuits within the integrated chips of which the video output circuit is formed.